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Integrated Circuit Systems, Inc.
ICS950219
Preliminary Product Preview
Programmable Timing Control HubTM for P4TM
Recommended Application: CK-408 clock for Intel(R) 845 chipset with P4 processor. Output Features: * 3 - Pairs of differential CPU clocks (differential current mode) * 4 - 3V66 @ 3.3V * 10 - PCI @ 3.3V * 1 - 48MHz @ 3.3V * 24-48 MHz selectable output @ 3.3V * 2 - REF @ 3.3V, 14.318MHz Features/Benefits: * Programmable output frequency. * Programmable output divider ratios. * Programmable output rise/fall time. * Programmable output skew. * Programmable spread percentage for EMI control. * Watchdog timer technology to reset system if system malfunctions. * Programmable watch dog safe frequency. * Support I2C Index read/write and block read/write operations. * Uses external 14.318MHz crystal. Key Specifications: * CPU Output Jitter <150ps * 3V66 Output Jitter <250ps * CPU Output Skew <100ps
Pin Configuration
*MULTISEL1/REF1 VDDREF X1 X2 GND *FS2/PCICLK0 *FS3/PCICLK1 PCICLK2 VDDPCI *FS4/PCICLK3 PCICLK4 PCICLK5 GND PCICLK6 PCICLK7 PCICLK8 PCICLK9 VDDPCI Vtt_PWRGD# RESET# GND *FS0/48MHz *FS1/24_48MHz AVDD48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF0/MULTSEL0* GND VDDCPU CPUCLKT2 CPUCLKC2 GND PD# CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 GND I REF AVDD GND VDD3V66 3V66_0 3V66_1 GND 3V66_2 3V66_3 SCLK SDATA
48-Pin 300-mil SSOP
* Internal Pull-up resistor of 120K to VDD
Frequency Table
Bit2 FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit7 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit6 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit5 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit4 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPUCLK MHz 102.00 105.00 108.00 111.00 114.00 117.00 120.00 123.00 126.00 130.00 136.00 140.00 144.00 148.00 152.00 156.00 160.00 164.00 166.66 170.00 175.00 180.00 185.00 190.00 66.80 100.20 133.60 200.40 66.66 100.00 200.00 133.33 3V66 MHz 68.00 70.00 72.00 74.00 76.00 78.00 80.00 82.00 72.00 74.30 68.00 70.00 72.00 74.00 76.00 78.00 80.00 82.00 66.66 68.00 70.00 72.00 74.00 76.00 66.80 66.80 66.80 66.80 66.66 66.66 66.66 66.66 PCICLK MHz 34.00 35.00 36.00 37.00 38.00 39.00 40.00 41.00 36.00 37.10 34.00 35.00 36.00 37.00 38.00 39.00 40.00 41.00 33.33 34.00 35.00 36.00 37.00 38.00 33.40 33.40 33.40 33.40 33.33 33.33 33.33 33.33
0640D--12/30/03 PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
ICS950219
Integrated Circuit Systems, Inc.
ICS950219
Preliminary Product Preview
General Description
The ICS950219 is a single chip clock solution for desktop designs using the Intel 845 chipset with PC133 or DDR memory. It provides all necessary clock signals for such a system. The ICS950219 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment. With all these programmable features ICS's, TCH makes mother board testing, tuning and improvement very simple.
Block Diagram
PLL2 /2
48MHz 24_48MHz REF (1:0)
X1 X2
XTAL OSC
PLL1 Spread Spectrum Control Logic
CPU DIVDER
3 3
CPUCLKT (2:0) CPUCLKC (2:0) PCICLK (9:0) 3V66 (3:0) RESET# I REF
PCI DIVDER
10
PD# MULTSEL(1:0) FS (4:0) SDATA SCLK Vtt_PWRGD#
3V66 DIVDER
4
Config. Reg.
Power Groups
Pin Number AVDD 2 24 39 VDD 9, 18 32 46 GND 47 21 43 GND 5, 13 29 36 Description REF output, Crystal 48MHz fixed, Fixed PLL CPU Outputs, CPU PLL, CPU Master Clock, -PCI outputs 3V66 outputs CPU Outputs, IREF, MULTSEL
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Integrated Circuit Systems, Inc.
ICS950219
Preliminary Product Preview
Pin Description
P IN NUM BE R 1 REF1 2, 9, 18, 24, 32, 39, 46 3 4 5, 13, 21, 29, 36, 43, 47 6 PCI CLK0 FS3 * 7 PCI CLK1 FS4 * 10 PCI CLK3 17, 16, 15, 14, 12, 11, 8 19 20 27, 28, 30, 31 22 PCI CLK ( 9: 4, 2) Vtt_PWRGD# RESET# 3 V6 6 ( 3 : 0 ) FS0 * 48M Hz FS1 * 24_48M Hz 25 26 33 34 35 SDATA SCLK G ND AVDD I REF O UT O UT IN O UT O UT IN O UT IN O UT I/O IN PW R PW R O UT 3. 3V PCI clock out put 3. 3V PCI clock out put s This 5V tolerant LVTTL input is a level sensitive strobe used to determine when FS (4:0) and MULTISEL inputs are valid and are ready to be sampled (active low) Real time system reset signal for frequency value or watchdog timmer timeout. This signal is active low. 3. 3V Fixed 66M Hz clock out put s f or HUB Logic input f r equency select bit . I nput lat ched at pow er on. 3. 3V Fixed 48M Hz clock out put . Logic input f r equency select bit . I nput lat ched at pow er on. Select able 24 or 48 M Hz out put Data pin for I2C circuitry 5V tolerant Clock pin for I2C circuitry 5V tolerant G r ound f or CO RE PLL Pow er f or CO RE PLL 3. 3V nominal This pin est ablishes t he r ef er ence cur r ent f or t he CPUCLK pair s. This pin r equir es a f ixed pr ecision r esist or t ied t o gr ound in or der t o est ablish t he appr opr iat e cur r ent . Asynchr onous act ive low input pin used t o pow er dow n t he device int o a low pow er st at e. The int er nal clocks ar e disabled and t he VCO and t he cr yst al ar e st opped. The lat ency of t he pow er dow n w ill not be gr eat er t han 3ms. "Complementory" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. 3.3V LVTTL input for selecting the current multiplier for CPU outputs. 3. 3V, 14. 318M Hz r ef er ence clock out put . O UT IN 3. 3V PCI clock out put Logic input f r equency select bit . I nput lat ched at pow er on. O UT IN 3. 3V PCI clock out put Logic input f r equency select bit . I nput lat ched at pow er on. VDD X1 X2 G ND FS2 * O UT PW R IN O UT PW R IN 3. 3V, 14. 318M Hz r ef er ence clock out put . 3. 3V pow er supply Cr yst al input , has int er nal load cap ( 33pF) and f eedback r esist or f r om X2 Cr yst al out put , nominally 14. 318M Hz. Has int er nal load cap ( 33pF) G r ound pins f or 3. 3V supply Logic input f r equency select bit . I nput lat ched at pow er on. P IN NAM E MULTSEL1 * T YPE IN DE S CRIP T IO N 3.3V LVTTL input for selecting the current multiplier for CPU outputs.
23
42 44, 40, 37 45, 41, 38 48
PD# CPUCLKC (2:0) CPUCLKT (2:0)
IN O UT O UT IN O UT
MULTSEL0 * REF0 * Internal pull-up resistor of 120K to VDD.
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Integrated Circuit Systems, Inc.
ICS950219
Preliminary Product Preview
Maximum Allowed Current
Max 3.3V supply consumption Max discrete cap loads, Vdd = 3.465V All static inputs = Vdd or GND 40mA 360mA
Condition Powerdown Mode (PWRDWN# = 0) Full Active
CPUCLK Swing Select Functions
MULTSEL0 0 0 0 0 1 1 1 1 MULTSEL1 0 0 1 1 0 0 1 1 Board Target Trace/Term Z 60 ohms 50 ohms 60 ohms 50 ohms 60 ohms 50 ohms 60 ohms 50 ohms Reference R, Iref= Vdd/(3*Rr) Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Output Current Ioh = 5*Iref Ioh = 5*Iref Ioh = 6*Iref Ioh = 6*Iref Ioh = 4*Iref Ioh = 4*Iref Ioh = 7*Iref Ioh = 7*Iref Voh @ Z, Iref=2.32mA 0.71V @ 60 0.59V @ 50 0.85V /2 60 0.71V @ 50 0.56V @ 60 0.47V @ 50 0.99V @ 60 0.82V @ 50
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv)
Ioh = 5*Iref Ioh = 5*Iref Ioh = 6*Iref Ioh = 6*Iref Ioh = 4*Iref Ioh = 4*Iref Ioh = 7*Iref Ioh = 7*Iref
0.75V @ 30 0.62V @ 20 0.90V @ 30 0.75V @ 20 0.60 @ 20 0.5V @ 20 1.05V @ 30 0.84V @ 20
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Integrated Circuit Systems, Inc.
ICS950219
Preliminary Product Preview
General I2C serial interface information How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
*See notes on the following page.
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Integrated Circuit Systems, Inc.
ICS950219
Preliminary Product Preview
Byte 0: Functionality and frequency select register (Default=0)
Bit Bit2 Bit7 Bit6 Bit5 FS4 FS3 FS2 FS1 Bit4 FS0 CPUCLK MHz Description 3V66 MHz PCICLK MHz 34.00 35.00 36.00 37.00 38.00 39.00 40.00 41.00 36.00 37.10 34.00 35.00 36.00 37.00 38.00 39.00 40.00 41.00 33.33 34.00 35.00 36.00 37.00 38.00 33.40 33.40 33.40 33.40 33.33 33.33 33.33 33.33 Spread % +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread +/-0.25% Center spread 0 to -0.6% Down spread 0 to -0.6% Down spread 0 to -0.6% Down spread 0 to -0.6% Down spread PWD
Bit (2,7:4)
Bit 3 Bit 1 Bit 0
0 0 0 0 0 102.00 68.00 0 0 0 0 1 105.00 70.00 0 0 0 1 0 108.00 72.00 0 0 0 1 1 111.00 74.00 0 0 1 0 0 114.00 76.00 0 0 1 0 1 117.00 78.00 0 0 1 1 0 120.00 80.00 0 0 1 1 1 123.00 82.00 0 1 0 0 0 126.00 72.00 0 1 0 0 1 130.00 74.30 0 1 0 1 0 136.00 68.00 0 1 0 1 1 140.00 70.00 0 1 1 0 0 144.00 72.00 0 1 1 0 1 148.00 74.00 0 1 1 1 0 152.00 76.00 0 1 1 1 1 156.00 78.00 1 0 0 0 0 160.00 80.00 1 0 0 0 1 164.00 82.00 1 0 0 1 0 166.60 66.66 1 0 0 1 1 170.00 68.00 1 0 1 0 0 175.00 70.00 1 0 1 0 1 180.00 72.00 1 0 1 1 0 185.00 74.00 1 0 1 1 1 190.00 76.00 1 1 0 0 0 66.80 66.80 1 1 0 0 1 100.20 66.80 1 1 0 1 0 133.60 66.80 1 1 0 1 1 200.40 66.80 1 1 1 0 0 66.66 66.66 1 1 1 0 1 100.00 66.66 1 1 1 1 0 200.00 66.66 1 1 1 1 1 133.33 66.66 0 - Frequency is selected by hardware select, latched inputs 1 - Frequency is selected by Bit 2,7:4 0 - Normal 1 - Spread spectrum enable 0 - Watch dog safe frequency will be selected by latch inputs 1 - Watch dog safe frequency will be programmed by Byte 10 bit
Note 1
0 0 (4:0) 0
Notes: 1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
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Integrated Circuit Systems, Inc.
ICS950219
Preliminary Product Preview
Byte 1: Output Control Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin# 45,44 38,37 41,40 PWD 1 1 1 X X X X X Description CPUT/C2 CPUT/C1 CPUT/C0 FS4 Read back FS3 Read back FS2 Read back FS1 Read back FS0 Read back
Byte 2: Output Control Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin# 17 16 15 14 12 11 10 PWD 1 1 1 1 1 1 1 1 Description Reserved PCICLK_9 PCICLK_8 PCICLK_7 PCICLK_6 PCICLK_5 PCICLK_4 PCICLK_3
Byte 3: Output Control Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin# 23 22 8 7 6 PWD 1 1 1 X 0 1 1 1 Description 48MHz_1 48MHz_0 Reset gear shift detect 1 = Enable, 0 = Disable Reserved Sel 24_48 MHz; 0 = 24 MHz, 1 = 48 MHz PCICLK_2 PCICLK_1 PCICLK_0
Byte 4: Output Control Register (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 31 30 48 1 27 28 PWD X X 1 1 1 1 1 1 Description MultiSEL0 (read back) MultiSEL1 (Read back) 3V66-0 3V66-1 REF0 REF1 3V 66_3 3V 66_2
Notes: 1. PWD = Power on Default 2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC off, and external resistor termination will bring CPUCLKC low.
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Integrated Circuit Systems, Inc.
ICS950219
Preliminary Product Preview
Byte 5: Programming Edge Rate (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# X X X X X X X PWD 1 1 1 1 1 1 1 0 Description (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Async. 3V66/PCI control bit 1 Async. 3V66/PCI control bit 0
Asynchronous 3V66/PCI Frequency Selection Table
B5 bit 1 B 5 bi t 0 = 0 B 5 bi t 0 = 1
0 66.01MHz/33.00MHz (Async with CPU) 75.44MHz/37.72MHz (Async with CPU)
1 66.66MHz/33.33MHz (Sync with CPU) 88.01MHz/44.01MHz (Async with CPU)
Byte 6: Vendor ID Register (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Revision ID Bit3 Revision ID Bit2 Revision ID Bit1 Revision ID Bit0 Vendor ID Bit3 Vendor ID Bit2 Vendor ID Bit1 Vendor ID Bit0
PWD X X X X 0 0 0 1
Description Revision ID values will be based on individual device's revision (Reserved) (Reserved) (Reserved) (Reserved)
Byte 7: Revision ID and Device ID Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Device ID7 Device ID6 Device ID5 Device ID4 Device ID3 Device ID2 Device ID1 Device ID0
PWD Description 0 0 1 Device ID values will be based on individual device 0 "28H" in this case. 1 0 0 0
Byte 8: Byte Count Read Back Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
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Name Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0
PWD Description 0 0 0 Note: Writing to this register will configure byte count and how 0 many bytes will be read back, default is 0FH = 15 bytes. 1 1 1 1
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Integrated Circuit Systems, Inc.
ICS950219
Preliminary Product Preview
Byte 9: Watchdog Timer Count Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
PWD Description 0 0 0 The decimal representation of these 8 bits correspond to X * 0 290ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 1 8 * 290ms = 2.3 seconds. 0 0 0
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Program Enable WD Enable WD Alarm S F4 S F3 S F2 S F1 S F0
PWD 0 0 0 0 1 0 0 0
Description Programming Enable bit 0 = no programming. Frequencies are selected by HW latches or Byte0 1 = enable all I2C programing. Watchdog Enable bit. This bit will over write WDEN latched value. 0 = disable, 1 = Enable. Watchdog Alarm Status 0 = normal 1= alarm status Watchdog safe frequency bits. Writing to these bits will configure the safe frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Ndiv 8 Mdiv 6 Mdiv 5 Mdiv 4 Mdiv 3 Mdiv 2 Mdiv 1 Mdiv 0
PWD X X X X X X X X
Description N divider bit 8
The decimal respresentation of Mdiv (6:0) corresposd to the reference divider value. Default at power up is equal to the latched inputs selection.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
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Name Ndiv 7 Ndiv 6 Ndiv 5 Ndiv 4 Ndiv 3 Ndiv 2 Ndiv 1 Ndiv 0
PWD Description X X X The decimal representation of Ndiv (8:0) correspond to the X VCO divider value. Default at power up is equal to the latched inputs selecton. Notice Ndiv 8 is located in Byte 11. X X X X
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Integrated Circuit Systems, Inc.
ICS950219
Preliminary Product Preview
Byte 13: Spread Spectrum Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name SS 7 SS 6 SS 5 SS 4 SS 3 SS 2 SS 1 SS 0
PWD Description X X The Spread Spectrum (12:0) bit will program the spread X precentage. Spread precent needs to be calculated based on the X VCO frequency, spreading profile, spreading amount and spread X frequency. It is recommended to use ICS software for spread X programming. Default power on is latched FS divider. X X
Byte 14: Spread Spectrum Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Reserved Reserved Reserved SS 12 SS 11 SS 10 SS 9 SS 8
PWD X X X X X X X X
Description Reserved Reserved Reserved Spread Spectrum Bit 12 Spread Spectrum Bit 11 Spread Spectrum Bit 10 Spread Spectrum Bit 9 Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name CPUDIV3 CPUDIV2 CPUDIV1 CPUDIV0 CPU Div 3 CPU Div 2 CPU Div 1 CPU Div 0
PWD X X X X X X X X
Description CPU2 clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider. CPU(1:0) clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
Byte 16: Output Divider Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name 3V66 Div 3 3V66 Div 2 3V66 Div 1 3V66 Div 0 3V66 Div 3 3V66 Div 2 3V66 Div 1 3V66 Div 0
PWD X X X X X X X X
Description 3V66(3:2) clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider. 3V66(1:0) clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
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ICS950219
Preliminary Product Preview
Byte 17: Output Divider Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name 3V66(3:2)_INV 3V66(1:0)_INV CPU_INV CPU_INV
PCI Div 3 PCI Div 2 PCI Div 1 PCI Div 0
PWD X X X X X X X X
Description 3V66(3:2) Phase Inversion bit 3V66(1:0) Phase Inversion bit CPUCLK_2 Phase Inversion bit CPUCLK Phase Inversion bit
PCI clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 2. Default at power up is latched FS divider.
Table 1
Table 2
Div (3:2) Div (1:0) 00 01 10 11
00 /2 /3 /5 /7
01 /4 /6 /10 /14
10 /8 /12 /20 /28
11 /16 /24 /40 /56
Div (3:2) Div (1:0) 00 01 10 11
00 /4 /3 /5 /9
01 /8 /6 /10 /18
10 /16 /12 /20 /36
11 /32 /24 /40 /72
Byte 18: Group Skew Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name CPU_Skew 1 CPU_Skew 0 Reserved Reserved CPU_Skew 1 CPU_Skew 0 Reserved Reserved PWD 0 1 0 0 0 1 0 0 Description These 2 bits delay the CPUCLKC/T2 with respect to CPUCLKC/T (1:0) 00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps Reserved Reserved These 2 bits delay the CPUCLKC/T (1:0) clock with respect to CPUCLKC/T2 00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps Reserved Reserved
Byte 19: Group Skew Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name These 4bits control CPU-3V66(3:2)
PWD 0 1 0 0 0 1 0 0 0 0 1 1 1 1 0 1 0 1 1 1 0 0 0 0 0 1
Programming Sequence 0 0 0 0 1 0 0ps 150ps 300ps 450ps 600ps 750ps Reserved Reserved Reserved Reserved Reserved Reserved
These 4 bits control CPU-3V66(1:0)
1 1 1 1 900ps Reserved Reserved Reserved
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ICS950219
Preliminary Product Preview
Byte 20: Group Skew Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name These 4bits control CPU-PCI(9:0)
PWD 1 0 0 0 1 0 0 0 0 0 1 1 1 1 0 1 0 1 1 1 0 0 0 0 0 1
Programming Sequence 0 0 0 0 1 0 0ps 150ps 300ps 450ps 600ps 750ps Reserved Reserved Reserved Reserved Reserved Reserved
Resreved
1 1 1 1 900ps Reserved Reserved Reserved
Byte 21: Slew Rate Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name PCICLK_2_Slew 1 PCICLK_2_Slew 1 PCICLK (1:0)_Slew 0 PCICLK (1:0)_Slew 0 3V66 (3:2)_Slew 1 3V66 (3:2)_Slew 1 3V66 (1:0)_Slew 1 3V66 (1:0)_Slew 0
PWD 1 0 1 0 1 0 1 0
Description PCICLK2 clock slew rate control bits. 01 = strong:11 = normal; 10 = weak PCICLK(1:0) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak 3V66 (2:1) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak 3V66 (1:0) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak
Byte 22: Slew Rate Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name REF Slew 1 REF Slew 0 PCI (9:7) Slew 1 PCI (9:7) Slew 0 PCI (6:5) Slew 1 PCI (6:5) Slew 0 PCI (4:3) Slew 1 PCI (4:3) Slew 0 PWD 1 0 1 0 1 0 1 0 Description REF clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak PCI (9:7)) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak PCI (6:5) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak PCI (4:3) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak
Byte 23: Slew Rate Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Reserved Reserved Reserved Reserved 48MHz Slew 1 48MHz Slew 0 24_48MHz Slew 1 24_48MHz Slew 0
PWD Description X X Reserved 1 0 1 48MHz clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak 0 1 24_48MHz clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak 0
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Integrated Circuit Systems, Inc.
ICS950219
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0C to +70C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5% PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Pin Inductance Input Capacitance 1 Transition Time 1 Settling Time1 Clk Stabilization1 Delay
1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP IDD3.3PD Fi L pin CIN Cout C INX Ttrans Ts TSTAB tPZH,tPZH tPLZ,tPZH
CONDITIONS
MIN 2 VSS-0.3
TYP
MAX VDD+0.3 0.8 5
UNITS V V mA mA mA mA mA mA mA MHz nH pF pF pF mS mS mS nS nS
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66M CL = Full load IREF=2.32 IREF= 5mA VDD = 3.3 V; Logic Inputs Out put pin capacitance X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. output enable delay (all outputs) output disable delay (all outputs)
-5 -5 -200
100 360 25 45 14.318 7 5 6 27 36 45 3 3 3 1 1 10 10
Guarenteed by design, not 100% tested in production.
0640D--12/30/03
13
Integrated Circuit Systems, Inc.
ICS950219
Preliminary Product Preview
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo1 VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm CONDITIONS VO = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 200MHz nominal 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V MIN 3000 660 -150 -300 250 770 5 756 -7 350 12 -300 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 4.8735 5.8732 7.3728 9.8720 175 175 850 mV 150 1150 550 140 300 5.0015 5.0266 6.0018 6.0320 7.5023 5.4000 10.0030 10.0533 mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps 1 1 1 1 1 1,2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 1 TYP MAX UNITS NOTES 1 1
Average period
Tperiod
Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle
Tabsmin tr tf d-tr d-tf dt3
332 344 30 30
700 700 125 125
Measurement from differential 45 49 55 % wavefrom tsk3 VT = 50% Skew 8 100 ps Measurement from differential tjcyc-cyc 60 150 ps Jitter, Cycle to cycle wavefrom 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz
0640D--12/30/03
14
Integrated Circuit Systems, Inc.
ICS950219
Preliminary Product Preview
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3 V +/-5%; C L = 10-30 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL F0
1
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 33.33
MAX 55 0.55 -33 38 2 2 55 500 250
UNITS MHz V V mA mA ns ns % ps ps
RDSN11 VOH1 VOL1 IOH1 IOL1 tr11 tf11 d t11 tsk11 tjcyc-cyc1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =10-30 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL FO1 RDSP11 VOH1 VOL1 IOH1 IOL1 tr11 tf11 d t11 tsk11 tjcyc-cyc1 VO = VDD*(0.5) IOH = -1 mA
CONDITIONS
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 66.66
MAX 55 0.4 -33 38 2 2 55 250 250
UNITS MHz V V mA mA ns ns % ps ps
IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
Guaranteed by design, not 100% tested in production.
0640D--12/30/03
15
Integrated Circuit Systems, Inc.
ICS950219
Preliminary Product Preview
Electrical Characteristics - 48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; C L = 10-30 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current 48DOT Rise Time 48DOT Fall Time VCH 48 USB Rise Time VCH 48 USB Fall Time 48 DOT to 48 USB Skew Duty Cycle Jitter
1
SYMBOL FO1 RDSN11 VOH1 VOL1 IOH1 IOL1 tr11 tf11 tr1 tf1 tskew 1 d t11 tjcyc-cyc1 VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA
CONDITIONS
MIN 12 2.4
TYP 48.008
MAX 55 0.55
UNITS MHz V V mA mA ns ns ns ns ns % ps
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT=1.5V VT = 1.5 V VT = 1.5 V
-29 29 0.5 0.5 1 1
-23 27 1 1 2 2 1
45
55 350
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3 V +/-5%; C L =10-20 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL FO RDSP11 VOH1 VOL1 IOH1 IOL1 tr11 tf11 d t11 tjcyc-cyc VO = VDD*(0.5) IOH = -1 mA
CONDITIONS
MIN 20 2.4 -29 29 1 1 45
TYP 14.318
MAX 60 0.4 -23 27 4 4 55 1000
UNITS MHz V V mA mA ns ns % ps
IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
Guaranteed by design, not 100% tested in production.
0640D--12/30/03
16
Integrated Circuit Systems, Inc.
ICS950219
Preliminary Product Preview
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
0640D--12/30/03
17
Integrated Circuit Systems, Inc.
ICS950219
Preliminary Product Preview
Un-Buffered Mode 3V66 & PCI Phase Relationship All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci.
3V66 PCICLK_F and PCICLK Tpci
Group Skews at Common Transition Edges: (Un-Buffered Mode)
GROUP 3V66 PCI 3V66 to PCI
1
SYMBOL CONDITIONS 3V66 3V66 pin to pin skew PCI PCI_F and PCI pin to pin skew S3V66-PCI 3V66 leads 33MHz PCI
MIN 0 0 1.5
TYP
MAX UNITS 500 ps 500 ps 3.5 ns
Guarenteed by design, not 100% tested in production.
0640D--12/30/03
Integrated Circuit Systems, Inc.
ICS950219
Preliminary Product Preview
N
c
SYMBOL
L
INDEX AREA
E1
E
12 D h x 45
a
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS950219yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0640D--12/30/03

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